This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-200253, filed Jun. 30, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a semiconductor memory having a DDR (double data rate) transfer technique.
2. Description of the Related Art
Recently, there are greatly increasingly demands on improving the processing speed of computer systems. In order to meet such demands, a synchronous DRAM (DDR-SDRAM) is presently being developed. The synchronous DRAM uses a DDR (double data rate) transfer technique, which transfers data between the memory and the CPU effectively at double the speed of a conventional technique, by synchronizing the transfer of data in synchronism with both of the leading edge and trailing edge of clock signals supplied for controlling the operation timing.
In the conventional synchronous DRAM (DDR-SDRAM), data is input/output by a DDR operation; however, various signals such as a row address strobe signal bRAS, a column address strobe signal bCAS, a chip select signal bCS, write enable signal bWE, bank select signals (BS0 and BS1), and row (column) address signals (A0 to A11) are not handled by the DDR operation. It should be noted that the first letter of each reference symbol, that is, b, indicates that the signal is of an inverted type.
Further, signals of row addresses and column addresses share address basses, input pins, input buffers and the like, and therefore they cannot be inputted at the same time.
Due to the two points described above, there is the following problem. That is, gaps are created while transferring data, thereby deteriorating the effective data transfer rate, particularly in the case where random row accessing is carried out.
FIG. 1 is a diagram illustrating a read-out operation in an interleave where the latency of the CAS signal is 2, the burst length is 4 and the number of banks is 4 and FIG. 2 is a diagram illustrating a write operation in an interleave where the latency of the CAS signal is 2, the burst length is 4 and the number of banks is 4. Further, FIG. 3 is a diagram illustrating a read-out operation in an interleave where the latency of the CAS signal is 2, the burst length is 2 and the number of banks is 4 and FIG. 4 is a diagram illustrating a write operation in an interleave where the latency of the CAS signal is 2, the burst length is 2 and the number of banks is 4.
In order for avoiding such a problem that the data transfer rate described above is deteriorated, there is a technique which prepares address buses, input pins, input buffers and the like are provided separately and exclusively for row address and column address. According to this technique, row address and column address are input at the same time, and therefore the above-described problem can be easily solved. However, with this technique, the necessary area for forming address buses, input pins, input buffers and the like will become twice as large, thereby increasing the chip area. Therefore, it is difficult to put it into practice.
The present invention has been proposed in consideration of the above-described problems entailed to the conventional technique, and the object thereof is to provide a semiconductor memory capable of enhancing the data transfer efficiency and increasing the circuit operation speed without increasing its chip area.
In order to achieve the above-described object, there is provided, according to the first aspect of the present invention, a semiconductor memory comprising: a memory cell for storing data, the memory cell being designated by an address signal; an address fetch circuit for fetching the address signal for designating the memory cell in synchronism with both of a leading edge and a trailing edge of a clock signal, the clock signal for providing timing for access to the memory cell; and a command circuit for fetching a command signal for instructing the access to the memory cell in synchronism with both of the leading edge and the trailing edge of the clock signal.
In order to achieve the above-described object, there is provided according to the second aspect of the present invention, a semiconductor memory comprising: a memory cell for storing data, the memory cell being designated by an address signal; a clock generating circuit for generating a clock signal used for providing timing for an access to the memory cell, the clock signal having a leading edge and a trailing edge; a first holding circuit for holding the address signal for designating the memory cell in synchronism with either one of a leading edge and a trailing edge of the clock signal; a second holding circuit for holding the address signal in synchronism with an other edge which comes after the one of edges, which is different from the one of the edges, used by the first holding circuit to hold the address signal; a first decoding circuit for decoding the address signal held by the first holding circuit; and a second decoding circuit for decoding the address signal held by the second holding circuit.
In order to achieve the above-described object, there is provided, according to the third aspect of the present invention, a semiconductor memory comprising: a memory cell for storing data; a clock generating circuit for generating a clock signal used for providing timing for an access to the memory cell, the clock signal having a leading edge and a trailing edge;
a first holding circuit for holding a command signal for instructing the access to the memory cell in synchronism with either one of the leading edge and the trailing edge of the clock signal; a second holding circuit for holding the command signal in synchronism with an other edge which comes after the one of edges, which is different from the one of the edges, used by the first holding circuit to hold the command; a first decoding circuit for decoding the command signal held by the first holding circuit; and a second decoding circuit for decoding the command signal held by the second holding circuit.
With the semiconductor memory having the above-described structure, not only input/output of data, but also the command signals, that is, the address signal, bank selection signal, row address strobe signal bRAS, column address strobe signal bCAS, chip select signal bCS and write enable signal bWE, are fetched in synchronism with both of the leading edge (the rising edge) and the trailing edge (the falling edge) of the clock signal. In this manner, it becomes possible to improve the effective data transfer rate. Further, not simply fetching these signals in synchronism with both of the leading edge and the trailing edge of the clock signal, but each signal is handled in accordance with its role of the signal, that is, for example, the handling of some signals is limited such that they are fetched in synchronism with leading edges of external clock signals, while others are fetched in synchronism with trailing edges of external clock signals. In this manner, the number of signals input from outside can be reduced. Thus, the circuit can be simplified in structure, and the chip area can be reduced and the circuit operation speed can be increased.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.